Date: 06/11/2012

New version of Riviera-PRO deliver 20% VHDL simulation performance gain

Aldec has released mixed language advanced verification platform, Riviera-PRO 2012.10 supporting latest versions of industry-standard SystemVerilog verification libraries, new language constructs, new debugging tools, and improved interfaces to other industry leading EDA tools.

Riviera-PRO is claimed to deliver a 20% VHDL simulation performance gain over previous releases. “We keep developing and delivering not only new productivity features, but also innovative core engine optimizations to boost simulation performance in VHDL and SystemVerilog to support the complexity and capacity of today’s designs,” said Mariusz Dykierek, Aldec R&D Project Manager. “Easy-to-use debugging tools and a powerful mixed language simulation engine are in high demand. Aldec continues to help our customers reduce design cost and time and bring their products to market quickly.”

Highlights of Riviera-PRO 2012.10:

Core Simulation Engine
Simulation performance improvements – VHDL simulation now up to 20% faster!
New language constructs in SystemVerilog’2009 and VHDL’2008
Support for the latest verification libraries – UVM 1.1c, SystemC 2.3.0, OS-VVM
Increase Stability on large multi-million gate designs

Framework and Productivity
Waveform enhanced for displaying of composite objects (virtual arrays)
Possibility to rename objects in the waveform, and context search
Additional operations using the drag-n-drop method

3rd Party Interfaces
The new way to use MATLAB co-simulation interface – Invoke Riviera-PRO from MATLAB
The latest precompiled simulation libraries for Altera and Xilinx FPGAs
Compatibility with the latest release of Xilinx Vivado Design Suite supporting Virtex-7
FSDB updated to the version 5.0 – Compatible with Verdi3 2012.07

Availability: Riviera-PRO 2012.10 is available today. Download the latest release from http://www.aldec.com/downloads. Current customers with valid maintenance receive the release at no additional cost.