Date: 25/10/2012

BW engine IC features random access performance for 100/200/400G n/w applications

MoSys has announced a new second-generation Bandwidth Engine IC optimized for advanced random access performance of 100G, 200G and 400G networking applications. The device is based on a dual-ported, single-bank, partitioned architecture that largely cuts random access cycle time, permitting a dramatic rise in the processing rate capability of networking equipment. The Bandwidth Engine family of ICs is designed and built for high reliability, carrier-grade applications.

The new device MSR720 extends Bandwidth Engine capabilities through the ability to simultaneously read and write to a specific memory location. The device architecture maintains full data coherency, high command efficiency and simplified scheduling, resulting in a performance of up to 4.5 Giga-Accesses per second (GA/s). The high access rates and decreased effective cycle time of the MSR720 access device are suited to the requirements of state memory and queuing applications, where repeat access of the same address is needed.

Using 16 SerDes lanes at 15 Gigabits per second (Gbps), the MSR720 interface operates at 480 Gbps, offering the host with up to 270 Gbps CRC protected, effective data throughput. The device also supports 36-bit half-word write capabilities which enhance the command bus utilization. The culmination of these features improves performance beyond the capability of standard memory subsystems, while occupying less board area, using fewer interface pins, and consuming less power.

Network system access rate requirements exceed the access rate at which traditional solutions can allow real-time access to packet header data. The second generation Bandwidth Engine architecture closes this performance gap for customers with its MSR720 device architecture and will deliver on these requirements.

"Our second generation Bandwidth Engine architecture will support purpose-built variants to optimize specific applications and access types," stated John Monson. "The addition of true random access functionality and faster effective cycle time in the MSR720 will deliver leading-edge performance in high data rate, low latency networking applications such as state memory, queuing and scheduling."

MoSys' Bandwidth Engine family of ICs uses the GigaChip Interface, an open, 90 percent efficient, reliable transport protocol optimized for chip-to-chip communications. The device is compatible with CEI-11G and XFI SerDes which permits a seamless interface with high performance FPGAs, as well as standard libraries available from ASIC providers. A complete package of RTL and tools is available to support the Bandwidth Engine interface.

The device is available for volume production now.

Source: Mosys