Date: 10/10/2012
14-bit, 250-MSPS, dual channel A/D converter from Analog features JESD204B
Analog Devices, Inc. has introduced the AD9250 dual-channel, 14-bit, 250-MSP A/D converter featuring the JEDEC JESD204B serial output data interface standard. The AD9250 A/D converter is offered with full JESD204B Subclass 1 deterministic latency at 250 MSPS. This functionality contains the precise synchronization of multiple data-conversion channels through a serial interface.
The AD9250 device’s serial interface implementation offers up to 5 Gbps over a 1 or 2 lane-capable link. Two serial lanes are used to support the full 250-MSPS, dual A/D converter data rate, or a single lane can be used to support decreased sampling rates.
“Xilinx is fully-committed to supporting the JEDEC JESD204B standard and is striving to accelerate adoption of the serialized interconnect technology for data converters. We are doing this by providing high quality, flexible, scalable and programmable IP to interface with high speed data converters like the AD9250,” said Sunil Kar, senior director, Wireless Business Group at Xilinx. “Xilinx currently provides JEDEC JESD204B IP for Subclass 0, 1 and 2 functionality, with line rates up to 10.3 GBPS and lane widths ranging from x1 to x8 on our devices. This combination of technology advancements improves system modularization, lowers cost and complexity and will enhance the capabilities and capacities of next generation wireless and wired networks.”
“This flagship product from Analog Devices signals a new, tightly integrated approach to designing the analog signal chain in FPGA-based systems,” said Kevin Kattmann, product line director, High-speed A/D Converters at Analog Devices. “The AD9250 dual 14-bit A/D converter delivers unmatched wideband signal processing performance while its simplified interface breaks design barriers for next-generation FPGA-based applications in software-defined radio and medical ultrasound. For many system designers, the I/O challenge in implementing the high-performance analog signal chain now has an elegant solution.”
The AD9250 converter’s JESD204B serial interface decreases the number of high-speed differential output data paths needed from as many as 28 to just two per IC. Its Subclass 1 deterministic latency function is repeatable from power-up cycle to power-up cycle and across link re-synchronization events. Areas where this function is important are in diversity radio systems and instrumentation, multi-mode digital receiver applications such as TD-SCDMA, WCDMA, LTE (especially the 2R2T >8R8T evolution), radar/defense electronics, medical imaging systems, cable infrastructure and general-purpose software radios.
Features:
1. JESD204B coded serial digital output
2. SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS
3. SFDR = 88 dBc at 185 MHz AIN and 250 MSPS
4. IF sampling frequencies of up to 400 MHz
5. 95-dB channel isolation/cross talk
Evaluation kits:
The AD9250-250EBZ (250 MSPS), AD9250-170EBZ (170 MSPS), and AD6673-250EBZ DUT boards, and companion HSC-ADC-EVALDZ high-speed data capture card, contains a signal performance-optimized complete evaluation system for the AD9250. The captured data can be analyzed using a laptop computer and ADI’s free VisualAnalog software. For compatibility with FPGA development platforms, the CVT-ADC-FMC-INTPZB FMC interposer connector for the DUT boards is available.
A 170-MSPS pin-compatible version (AD9250-170) is available, as well as the AD6673, an 11-bit, 250-MSPS, pin-compatible version.
Product Sample availability Production delivery Price Packaging
AD9250-250 Now Stock $131.57 (1k qty) 48-lead LFCSP
AD9250-170 Now Stock $72.50 (1k qty) 48-lead LFCSP
AD6673-250 Now Stock $74.80 (1k qty) 48-lead LFCSP
AD9250-250EBZ - Stock $350.00 -
AD9250-170EBZ - Stock $300.00 -
AD6673-250EBZ - Stock $300.00 -
HSC-ADC-EVALDZ - Stock $750.00 -
CVT-ADC-FMC-INTPZB - Stock $99.00 -
Download data sheet: http://www.analog.com/AD9250
Source: Analog Devices