Date: 15/07/2012

40GbE100GbE Ethernet IP cores from Altera

Altera has announced the production availability of its 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) cores. These cores target chip-to-optical module, chip-to-chip, and backplane applications. The media access control (MAC) and physical coding sublayer plus physical media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba-2010 standard compliant, reducing design complexity for customers integrating 40GbE and 100GbE connections on Altera’s 28-nm Stratix V FPGAs and 40-nm Stratix IV FPGAs.

“As more system designs use Ethernet at high speeds—not only for local-area network attachment but to interconnect within systems—subsystem IP, including 40GbE/100GbE MAC and PCS+PMA layers, becomes a vital component in the system design team’s toolkit,” said Vince Hu, vice president of corporate and product marketing. “These cores, optimized for integration with Altera development kits and Altera’s Quartus II software v12.0, create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs.”

The 40GbE and 100GbE MAC and PHY IP cores provide an interface composed of a single packet-based channel that is logically compatible with previous-generation Ethernet systems. The cores are supported in Altera’s Stratix V GT and GX FPGAs with transceivers operating at data rates up to 28.05 Gbps and 14.1 Gbps, respectively, and Stratix IV GT FPGAs with transceivers operating at data rates up to 11.3 Gbps. Stratix FPGAs combine high density, high performance and a rich feature set, allowing customers to integrate more functions and maximize system bandwidth.

Altera's 40GbE and 100GbE IP cores are available for separate download from Altera.com and are compatible with the recently announced Quartus II software v12.0. For more information on Altera’s 40GbE and 100GbE IP cores visit www.altera.com/40-100GbE