Date: 15/07/2012

Synopsys' PCI Express controller IP taped out in multiple designs

Synopsys has announced that its industry-first PCI Express controller IP with support for low-power sub-states has successfully taped out in multiple designs. Synopsys says the addition of the L1.1 ("snooze") and L1.2 ("off") sub-states to Synopsys' DesignWare controller IP for PCI Express 1.0, 2.0 and 3.0 enables designers to reduce power consumption in key market segments, including camera, card reader, networking and wireless applications serving the ultrabook and tablet markets. L1 sub-states reduce a PCI Express system's link idle power consumption from 15 to 20 milliwatts per lane to 10microwatts per lane, or by approximately 99 percent, by repurposing the signals between the PHY and the controller so that they turn off the high-speed circuits in the PHY when not in use, as per Synopsys.

"Reducing power consumption in every aspect of an SoC is key for a mobile design's success," said Eric Esteve, market analyst at IPnest. "The availability of L1 sub-states in PCI Express controller IP will enable lower power consumption, which in turn improves battery life—a key differentiator in today's mobile designs."

"With the availability of L1 sub-states in our DesignWare controller IP for PCI Express, Synopsys leads the industry in adopting and rolling out the latest PCI-SIG enhancements," said John Koeter, vice president of marketing for IP and systems at Synopsys. "Our complete PCI Express controller IP portfolio helps reduce designers' integration risk and development time. With our first-to-market rollout of L1 sub-states, the portfolio continues to be on the forefront of power conservation for mobile and consumer device designers using PCI Express."