Date: 05/07/2012

Newest version of the 68000 processor IP core from Digital Core Design

Digital Core Design has introduced the newest version of the Motorola’s 68000 16/32-bit microprocessor. D68000 is a low cost 32-bit MCU. Improved architecture enables this IP Core to run with uCLinux and hence can be used as HTTP server or FTP client.

The D68000 is 100% compatible with original Motorola’s 68000. As a proof to mention, a test run on classic Amiga 500+ computer showed that DCD’s CPU can be 1:1 replacement for original chip, as per Digital Core Design . But classic computers are not the target destination for the product, cause improved architecture, creates new possibilities.

D68000 runs with uCLinux Operating System and hence makes this IP Core solution for embedded servers, certified to be used only with m68k processors. The BOA application is used as HTTP server and effective communication could be established through FTP protocol. uCLinux is a MMU-less derivative of Linux Operating System adopted for embedded solutions. It offers all of the Linux benefits including stability, common Linux Kernel API, multitasking, full featured TCP/IP networking, Virtual File System and reduces the amount of memory needed by its kernel and running applications (it uses just 400kB).

DCD’s solution is offered with fully automated test-bench and complete set of tests, which permit package validation at each stage of SoC design flow. “We have built special testing platform to run D68000 with uCLinux Operating System”, explains Jacek Hanke, president of Digital Core Design. “And to make this IP Core more user friendly, it’s being equipped with DoCD-BDM hardware debugger”.

The new IP Core from DCD is a technology enables engineer to employ it in either ASIC, Altera, Lattice or Xilinx FPGA chips. The D68000 is binary-compatible with m68k family of microprocessors, has a 16-bit data bus and a 24-bit address data bus. Its code is compatible with the MC68008, upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. The difference lies in improved instructions set, which permits to execute a program with a higher performance, than the standard 68000 core can provide. MULS, MULU take just 28 clock periods, the same as DIVS, DIVU. Optimized shifts and rotations, combined with shorter effective address calculation time and removed idle cycles make this IP Core more power efficient.

The D68000 is developed with DoCD-BDM hardware debugger, which provides debugging capability not only for the IP Core, but for the whole SoC system. DCD’s debugger is 100% compatible with BDM debug interfaces, working with its interfaces/cables: Public Domain cable, Macraigor Wiggler and P&E BDM cable. DoCD’s are supported by standard debugging tools like GNU GD8 debugger, Cosmic ZAP debugger and Tasking debugger.

Source: Digital Core Design