Date: 26/06/2012

New version of 40 nm RTL-to-GDSII ref-design flow for SMIC foundry

Synopsys has made available version 5.0 of its 40-nanometer (nm) RTL-to-GDSII reference design flow for China based chip foundry SMIC.

This reference flow has automated clock mesh synthesis feature and gate array engineering change order (ECO) flow to prevent redesigns. The reference flow also includes support for low power techniques such as power-aware clock tree synthesis, power gating and physical optimization, driven by the IEEE 1801 low power design intent standard.

"Designers require a reference flow that addresses both high-performance and low power requirements," said Tianshen Tang, SMIC's vice president of design service. "With the release of SMIC-Synopsys Reference Flow 5.0, we are enabling IC designers to accelerate their designs into manufacturing through the combination of SMIC's 40nm process technology and Synopsys' technology-leading design solutions."

"Customers are looking for tools and methodologies that allow them to deliver designs that meet their unique performance goals and requirements," said Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys. "Through our collaboration with SMIC, we are able to provide our mutual customers a proven reference flow and immediate access to both high-performance and low power design solutions tailored for SMIC's 40-nanometer low power process."

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