Date: 07/06/2012

ICsense releases 1.8mA, 2.8 ps rms jitter fully integrated clean-up PLL

ICsense has developed a state-of-the-art low-power clean-up phase-locked loop (PLL) to provide synchronized and clock signals to high-accuracy sensing systems. The PLL synchronizes to and cleans up an incoming clock signal to provide a low power and stable clock signal.

The PLL is fully integrated on an area of 0.65mm2 and includes a ring oscillator, phase-frequency detection, a third order loop filter and a frequency divider. The ring oscillator is an advanced, differential and highly programmable architecture with measures to reduce white and 1/f related jitter. The power-jitter trade-off has been optimized to be close to the fundamental limits.

Features:
1. Full integration of 8MHz PLL
2. Power consumption: 1.8mA
3. Jitter: 2.8 ps rms
4. Phase noise: -135dBc/Hz at 400kHz
5. Spurious emission: < -90dBc
6. 0.18um CMOS technology
7. Junction temperature: -40°C to 100°C