Date: 07/06/2012

Complete SoC design solution from Synopsys for Samsung's 20nm node

Synopsys, Inc. has announced the availability of a complete solution to enable engineers to develop state-of-the-art System-on-Chip (SoC) designs at Samsung's 20-nanometer (nm) process geometry.

Samsung Electronics and Synopsys R&D teams built this solution including the tapeout of the first 20-nm chip based on Samsung's High-k metal gate process technology. The double-patterning enabled solution includes Synopsys' IC Compiler place and route solution, IC Validator physical verification product, StarRC extraction tool, and PrimeTime timing signoff tool and all the required technology files, runsets, and rundecks.

"20 nanometer will be a very important process node which could change the landscape of the semiconductor industry," said Dr. Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics. "Our 20 nanometer collaboration with Synopsys, starting with our first 20 nanometer test chip tapeout, has allowed us to bring the best of 20 nanometer process technology to our mutual customers. In addition, our product teams are currently developing several next-generation SoCs for our 20 nanometer node that rely on Synopsys' Galaxy Implementation Platform."

"Broad deployment of the Galaxy Implementation Platform at Samsung for 20nm designs is the result of the strategic collaboration between the two companies," said Dr. Antun Domic, senior vice president and general manager of Implementation Group, Synopsys, Inc. "We have worked closely to address the new challenges introduced by 20nm node including double patterning technology. The collaborative innovations between Samsung and Synopsys will enable designers to manage power, performance, area, and time-to-market constraints by taking advantage of 20nm process technology to bring their best products to market."

The Synopsys tools in the qualified flow include:
1. IC Compiler: Double-patterning aware placement, extraction and routing can deliver an optimal, DPT-compliant layout while minimizing any impact on area and performance
2. IC Validator: In-Design technology for fast detection and automatic repair of signoff-level DPT decomposition violations and yield detractor patterns, accelerating design closure for manufacturing compliance
3. PrimeTime: Added support for new multi-valued SPEF with minimal impact on runtime maintains signoff timing results at 20nm, including effects of double-patterning
4. StarRC: Silicon-calibrated modeling of parasitic variation addresses the effects of double patterning technology due to mask misalignment to enable accurate and high performance design

For details on Synopsys' 20-nanometer solution www.synopsys.com/20nm