Date: 07/06/2012

Integrated hybrid prototyping solution from Synopsys

Synopsys, Inc has announced an integrated hybrid prototyping solution that combines Synopsys' Virtualizer virtual prototyping and Synopsys' HAPS FPGA-based prototyping to accelerate the development of system-on-chip (SoC) hardware and software.

By using Virtualizer virtual prototyping for new design functions and HAPS FPGA-based prototyping for reused logic, designers can start software development up to 12 months earlier in the design cycle. In addition, Synopsys' hybrid prototyping solution enables designers to accelerate hardware/software integration and system validation, reducing the overall product design cycle.
Developers can partition their ARM-based deisgns into virtual and FPGA-based prototypes with models for ARM Cortex processors, ARM AMBA protocol-based transactors, and DesignWare IP.

"The rising complexity and software content associated with multi-core SoCs means that system engineers and software developers cannot wait for hardware to begin their work; so, they are increasingly utilizing prototypes of their chips and systems," said Chris Rommel, vice president, embedded software and hardware, of VDC Research. "Synopsys' 'hybrid' approach addresses many of the limitations of standalone SoC prototyping methods by allowing developers to freely mix pre-RTL transaction-level models with RTL that already exists or is being created, giving design teams a significant head start on their hardware and software development."

Synopsys' hybrid prototyping solution enhances software stack validation through high-speed execution of processors using a Virtualizer virtual prototype. It allows direct connection to real-world I/O model interfaces through analog PHYs or test equipment attached to a HAPS FPGA-based prototype. In addition, designers can take advantage of existing RTL or IP in the FPGA-based prototype and new functions in SystemC transaction-level models.

Synopsys' HAPS Universal Multi-Resource Bus (UMRBus) physical link efficiently transfers data between the virtual and FPGA-based prototyping environments. The pre-verified HAPS-based transactors, supporting ARM AMBA 2.0 AHB/APB, AXI3, AXI-4 and AXI4-Lite interconnects, give designers the flexibility to partition the SoC design between the virtual or FPGA-based prototyping environments at the natural block-level boundaries of the AMBA interconnect. By using the software debug capability within the Virtualizer-based environment in a hybrid prototype, users have greater visibility and control into the register and memory files of the software under development compared to traditional FPGA-based prototyping.

"Hybrid prototyping offers design teams the best of what both hardware and software prototyping have to offer," said John Koeter, vice president of marketing for IP and systems at Synopsys. "By integrating the strengths of Virtualizer virtual prototyping with HAPS FPGA-based prototyping using the UMRBus physical link, Synopsys enables designers to develop fully operational SoC prototypes much faster and earlier in the design cycle, and accelerate software development and full system validation."

The hybrid prototyping solution is available now to early adopters.