Date: 23/05/2012

New VHDL entry and inspection tool from Sigasi accelerates feedback cycle

Sigasi has launched a new version of its VHDL entry and inspection tool, Sigasi Pro 2.4. In response to user requests, this new version features integration with Riviera-PRO that enables users to automatically start the Aldec compiler with each file save. As a result, designers can see continuous, up-to date feedback from Riviera-PRO.

Sigasi's type time compiler notifies the designer of certain common errors as the code is typed, however this type-time error checker does not catch all errors. The new integration with Riviera-PRO delivers a new line of defence against bugs and flags all violations of the VHDL language in the code - enabling users to continue to leverage VHDL while delivering access to alternative debugging features.

"Those errors would never make it to tape-out," says Sigasi's CEO Philippe Faes. "But they would take up precious time from design engineers and verification engineers." The integration shortens the feedback cycle between man and machine (or between engineer and compiler). As a result, illegal RTL code will never survive longer than a few minutes, and will only take seconds to correct.

A demonstration video at: http://www.sigasi.com/aldec-integration