Date: 16/05/2012

New NVM Express IP solutions released by Cadence for SSD interface

Cadence Design Systems, Inc. has launched the IP subsystem for the development of SoCs supporting the NVM Express 1.0c standard. This is an interface technology used in the fast growing solid-state drive (SSD) market. The solution includes Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem. The subsystem features fully-integrated component IP, including the NVM Express Controller, firmware, and the corresponding NVMe and PCIe models from the Cadence Verification IP Catalog. This level of integration enables easy implementation of NVM Express in SoC designs.

NVM Express is a specification that speeds up the broader adoption of PCI Express-based solid state drives by improving performance, reducing power consumption and latency compared to existing SATA/SAS interfaces or proprietary PCI Express implementations. The NVM Express specification defines the register interface, command set, and feature set to provide a scalable interface for PCI Express-based SSDs.

"Our studies find that PCI Express is poised to become the preferred embodiment of NAND in the enterprise, and this will lead to expanding adoption of the NVM Express protocol," said Jim Handy, director, objective analysis. "Today several vendors produce PCI Express SSDs based on an SSD array architecture, but over time we expect these to yield to faster designs that remove the intervening step and allow NAND flash to communicate directly using an NVM Express interface, as supported by the Cadence suite."

"Cadence combined our expertise in interface IP, analog/mixed signal technologies, and system verification to offer customers a complete and full-featured NVM Express interface subsystem," said Martin Lund, senior vice president, research and development, SoC realization group, Cadence. "Without this subsystem approach, SoC designers would need to source their interface component IP separately and drive integration on their own, often increasing their design risk and overall development time for new SoCs."

The controller used in the Cadence NVM Express solution supports advanced command management, data tiering and hardware command acceleration. The included driver firmware offers an interface to the system firmware. The solution also includes a verification and test environment spanning from the PCI Express interface to the internal bus fabric.