Date: 13/05/2012
MIPS Technologies Introduces New Aptiv Microprocessor Cores
MIPS Technologies has introduced new microprocessor cores called Aptiv Generation cores. The Aptiv family includes proAptiv, interAptiv and microAptiv families.
Gideon Intrater, Vice President of Marketing, MIPS Technologies says "With the launch of our new Aptiv Generation of products, MIPS is entering a new era of innovation and increasing our competitive position. The Aptiv Generation is the result of strategic investments we have made, and are continuing to make for the future. We are pushing performance efficiency to new levels. Our previous generation of cores was already more performance-efficient than the competition. The new Aptiv Generation is even better. With these cores and the ever-expanding ecosystem around the MIPS architecture, we are providing solutions that will enable our customers to differentiate and win in an increasingly competitive market."
J. Scott Gardner, Senior Analyst, The Linley Group / Microprocessor Report says "Microprocessor technology continues to evolve to address rapidly-increasing demands for processing power across applications that range from low-power mobile devices to high-performance networking products. MIPS' new Aptiv Generation introduces a lineup of CPU cores with the performance and power efficiency to address this broad range of markets. The specs of the new proAptiv core in particular show it to be a major step forward in performance, dramatically improving CoreMark/MHz while maintaining the power and area efficiency that we have come to expect from the MIPS architecture."
Key features as shared by the MIPS:
proAptiv Family:
Leading high-end CPU performance efficiency delivering over 4.4 CoreMark/MHz and 3.5 DMIPS/MHz1 in considerably smaller area compared to competing IP cores2.
Ideal for applications processing in connected consumer electronics such as high-end mobile devices and "smart" home entertainment products, and control plane processing in networking applications.
Efficient top-end performance minimizes the need for exotic power management schemes such as "big.LITTLE" in many mobile applications
60-75% higher performance on CoreMark and DMIPS scores compared to MIPS32 74K/1074K superscalar single/multicore products.
Highly-scalable solution leveraging up to six cores connected in a multi-core Coherent Processing System (CPS)
High-performance multi-issue, deeply out-of-order (OoO) architecture with state-of-the-art branch prediction.
New higher-performance floating point unit (FPU) with higher synthesizable frequency for 1:1 clock with core and native double-precision execution.
Single-core and multi-core (up to six core) configurations
Performance-enhanced, tightly-integrated second generation Coherence Manager and L2 cache controller with lower total latency
MIPS Digital Signal Processing (DSP) Application Specific Extension (ASE) v2.
Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3GB+ user space.
interAptiv Family:
The interAptiv core leverages a balanced nine-stage pipeline with multi-threading to deliver leading performance efficiency, achieving greater than 50% more CoreMark/MHz than competing cores in similar die area1,2.
Ideal for highly-parallel applications requiring cost and power optimization, such as smart gateways, baseband processing in LTE user equipment and small cells, SSD controllers and automotive equipment
Highly-scalable solution leveraging one or more threads per core, and up to four cores connected in a multi-core Coherent Processing System (CPS)
Multi-threaded pipeline implements dual virtual processors, appearing as two complete CPUs to an SMP Linux operating system.
Hardware Quality of Service (QoS), thread management support and inter-thread communication enable optimal control for real-time applications.
Performance-enhanced, tightly-integrated second generation Coherence Manager and L2 cache controller with lower total latency.
Support for up to two I/O coherency units.
Error Checking and Correction (ECC) support in L1 data cache, L2 cache and data SPRAM.
Enhanced Virtual Address (EVA) for efficient 32-bit address map utilization to reach 3GB+ user space.
Optional floating point unit
microAptiv Family:
Low-power, compact, real-time embedded processor core with integrated standard I/O interfaces, building on popular MIPS32 M14K core family with microMIPS code compression instruction set architecture
Integrates DSP and SIMD functionality to address signal processing requirements for a wide range of embedded segments including industrial control, smart meters, automotive and wired/wireless communications.
Leverages highly-efficient 5-stage pipeline to achieve 3.09 CoreMark/MHz and 1.57 DMIPS/MHz1 in microMIPS mode, with 40% and 25% higher performance, respectively, compared to competition2
MCU and MPU (with integrated cache controller/MMU) product versions available for microcontroller and embedded applications
Compared to previous generation MIPS cores and competitive cores, offers greater range of design features for both control and DSP operations.
New memory protection unit for enhanced program code and data security, microMIPS-only execution mode, secure debug and 2-wire cJTAG support.
Detailed product information including benchmarks, specifications, datasheets and more at www.mips.com/aptiv.
Availability: All Aptiv core families can be licensed now. The proAptiv family will be generally available in mid-2012 supporting a range of functional and performance points with single and multi-core versions. The new proAptiv FPU is also available. The interAptiv family will be available in mid-2012 in dual- and quad-core configurations, with optional FPU. Single core versions will be available in the fourth quarter. The microAptiv family is available now, with cache/MMU or non-cached core options.