Date: 02/05/2012

TripleCheck IP validator from Cadence for IP compliance testing

Cadence Design Systems has announced TripleCheck IP Validator to simplify and accelerate compliance testing of interface design IP. The IP Validator is an addition to the Cadence Verification IP (VIP) catalog that helps system and semiconductor companies verify their implementations of standard interfaces, such as PCI Express 3.0.

"PCI-SIG is the industry leading organization responsible for development and management of the PCI Express specification," said Al Yanes, president and chairman, PCI-SIG. "We are delighted that Cadence continues to advance the PCI Express 3.0 specification with their innovative verification IP products and methodologies."

The verification of standard interfaces are difficult because of the growing complexity. TripleCheck IP Validator addresses this issue by building on the earlier generations of Cadence compliance solutions: PureSuite and Compliance Management System (CMS).

"Feedback from hundreds of users over several years was used to shape TripleCheck," said Erik Panu, VP of research and development for verification IP, system and software realization group, Cadence. "Customers wanted the extensive directed tests that PureSuite provided, plus the constrained-random testing approach of CMS and its innovative vPlan, an interactive verification specification that correlates coverage from regression runs to the protocol specification, all based on the Universal Verification Methodology (UVM)."

IP Validator is currently available for PCIe Gen 3.