Date: 08/04/2012

6th ver. of Open Silicon's Interlaken IP core supports speeds up to 600 Gbps

Open-Silicon has announced 6th version of its Interlaken IP core with chip-to-chip interface speeds up to 600 Gbps. The updated version includes enhancements for increased configurability and flexibility and is offered in the flexible business model.

Open-Silicon Interlaken Controller IP Version 6 Features:

o Support for retransmit extension protocol introduced by the Interlaken Alliance in September 2011
o Support for up to 28G SerDes data rates
o Increased flexibility by allowing a single instance of the core to have multiple configurations (e.g. a single 600Gbps interface or four 150Gbps interfaces) selected at power-up
o Multiple user-data interface options 128bit or 256bit wide with one, two, or four segments

"Open-Silicon has actively participated in the Interlaken Alliance since its formation in 2007," said Fred Olsson, Interlaken Alliance co-founder. "The Alliance has since created multiple specifications to advance its mission of chip-to-chip interoperability for high-speed packet transfers. I am pleased to see Open-Silicon both take advantage of some of the most recent specification additions as well as drive the bandwidth higher."

"Open-Silicon remains committed to the Interlaken protocol and providing the highest-performance, most scalable Interlaken IP," said Aashish Malhotra, director of IP solutions, Open-Silicon."We see Interlaken as a standard that is growing from its roots of networking devices to new markets in need of scalable, high-performance, high-bandwidth interface solutions."


The Open-Silicon Interlaken Protocol Controller IP supports the following Interlaken Alliance specifications:
o Interlaken Protocol Definition, v1.2
o Interlaken Look-Aside Protocol Definition, v1.1
o Interlaken Interop Recommendations, v1.6
o Interlaken Retransmit Extension Protocol Definition v1.1

More info at http://www.open-silicon.com/ip-and-technology/open-silicon-ip/interlaken-controller-ip.html.

Open-Silicon also announced it has successfully integrated 25 Analog Bits IP cores into complex ASIC and SoC designs. The IP cores are silicon-proven down to 28nm and across various foundry processes, and meet Open-Silicon's stringent IP qualification requirements.