Date: 12/03/2012

Dual 100 Gbps Gearbox solution for CFP2 optical modules

Xilinx, Inc. has announced what it claims as industry's first dual 100 Gbps Gearbox solution for connecting 100G interfaces with the newest generation of high-density, 100 Gbps CFP2 optical modules. This implementation based on the Virtex-7 HT FPGA family with 28 Gbps transceivers, Xilinx says it can provide communications customers with twice the density and more advanced debugging features compared to competing devices as well as replace what would be a three chip ASSP design.

"The anticipated pace of growth in the 100G market provides an unprecedented opportunity in the optical transmission space for FPGA vendors to secure a domineering role in providing chips for a far-reaching period of time," said Mark Lutkowitz, Principal of Telecom Pragmatics. "Xilinx's Gearbox IP will be a key enabler in meeting the higher density and lower power demands for second-generation CFPs."

The Xilinx Dual 100G Gearbox solution includes the Gearbox IP cores for dual 100 Gbps channels supporting two CFP2 and future CFP4 optical modules and the Virtex-7 HT FPGA silicon (7VH290T, 7VH580T or 7VH870T). The solution maps data between the ten and four serial lane interfaces, in both ingress and egress directions. It converts data streams of either CAUI (10x 10.3125G) or OTL4.10 (10x 11.18G) to four lanes of proposed CAUI4 (4x 25.78G) or OTL4.4 (4x 27.95G). In the case of 100GE, the original twenty PCS lanes are reconstructed internally, allowing per-lane debug, skew insertion, and data manipulation, all under user control. Unique in the FPGA industry is the dedicated transceivers in the Virtex-7 HT Dual Gearbox devices that are pinned out to connect seamlessly with CFP2 optics without additional vias for crossovers to improve signal integrity, according to Xilinx.

"This new Xilinx offering of Dual 100 Gbps Gearbox IP cores and Virtex 7-HT FPGA silicon enables equipment vendors to connect their 100 Gbps interfaces with up to two CFP2 optical modules while lowering the overall BOM by reducing chip count and allowing integration with OTN framers as well as 100G bridges into a single chip," said Gilles Garcia, Director of Wired Communications at Xilinx. "Additionally, the programmability of the Virtex-7 HT FPGA ensures that the equipment vendors can easily stay abreast of the changes in standards that are still evolving in the optical, Ethernet and OTN market space."

For more information on Xilinx's Dual 100G Gearbox, download the 100G Dual Gearbox: Improving Port Density on Line Cards in Core Network Equipment white paper on Xilinx.com.