Date: 12/03/2012

RTL to GDS II flow from Cadence supports double patterning semiconductor tech

Cadence Design Systems, Inc. has introduced the latest release of Cadence Encounter RTL-to-GDSII flow for designing semiconductor chips at 20nm nodes, where semiconductor industry is using double patterning tech until the extreme ultraviolet lithography becomes reality. The new Encounter 20-nm methodology supports double-patterning.

This physical design tool for chip manufacturing covers floorplanning, placement and routing to signoff timing, power and physical verification. This tool also said to enhance die area efficiency of 20-nanometer double-patterning designs, and enables more efficient engineering change order (ECO) revisions. Enhancements to the Cadence Physical Verification System provide foundry-qualified 20-nanometer in-design checking and final signoff verification to ensure DRC and double patterning color correctness.

This latest release of the Encounter RTL-to-GDSII flow includes the new GigaOpt engine, which integrates key physical-aware synthesis technology with physical optimization for faster timing closure and better correlated results.

The new release also has GigaFlex tech to enable concurrent top-and-block hierarchical design and implementation, reducing iterations and total design cycle time.

Dr. Leo Li, president and CEO of the fast growing Spreadtrum finds this tool effective in designing ICs for low cost smart phones. Spreadtrum is a China based wireless semiconductor chip vendor for mobile phones whose revenue increased 94.7% from US$346.3 million in 2010 to US$674.3 million in 2011. Spreadtrum's big custromers include China bases telecom OEMs such as Huawei and ZTE. Cadence seems to have edge over other VLSI tool vendor in Chinese market.

For chips developed at 28nm and below whose development cost is high, the populous regions such China, India and South East Asia are going to be important markets for chips developed in deeper nodes.