Date: 19/01/2012

New book titled "Advanced Verification Topics" by Cadence for VLSI design

Cadence Design Systems, Inc. has published a new book titled "Advanced Verification Topics" for VLSI design community. This book written by Cadence' verification experts describes in detail the latest techniques and methodologies for verifying complex IP and systems on chips (SoCs). "Advanced Verification Topics" builds on the prior Cadence book, "A Practical Guide to Adopting the Universal Verification Methodology (UVM)." The new book covers topics such as metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM.

"With the march toward greater design complexity showing no sign of abating, comprehensive verification is essential for a company to achieve its profitability goals," said Hao Fang, IP design manager at LSI. "'Advanced Verification Topics' will be an important reference book for teams responsible for verifying complex mixed-signal IP and SoCs that utilize low-power, verification IP (VIP), transaction-level models (TLM), acceleration, and similar techniques to reduce risk while getting end products into working silicon faster."

The 229-page "Advanced Verification Topics" is available now at Amazon.com and Lulu.com.

"Cadence has long been at the forefront in advanced verification, and 'Advanced Verification Topics' is another leap forward for engineers facing the challenge of validating today's remarkably complex designs," said Boyd Donckels, vice president of research and development with the Silicon Realization Group at Cadence. "We are pleased to help verifications engineer working with complex IP and SoCs by sharing the combined knowledge and experience that has come from thousands of successful projects."