Date: 18/11/2011

Connectivity IP cores from Xilinx for LTE and LTE-A wireless base stations

Xilinx, Inc. has made available of three key connectivity IP cores Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP for designing chips used in 3G+/4G wireless base stations.

The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP is designed to the RapidIO Trade Association's RapidIO Gen 2.2 specification supporting line rates of up to 6.25G in 1x/2x/4x lane widths.

The CPRI v4.1 LogiCORE IP is designed to the Common Public Radio Interface (CPRI) standard specification v4.2 and is ideal for connectivity between Radio Equipment Controllers (REC) or baseband/channel cards and one or more Radio Equipment units (radio cards).

The Xilinx JESD204B v.1.1 LogiCORE IP is offered to replace wide parallel interface to data converters with 1/2/4 high speed serial interface links to overcome I/O constraints and PCB layout cost and complexity.

Pricing and Availability: TheSerial RapidIO Gen 2 v1.2, CPRI v4.1, and JESD204B v1.1 LogiCORE IP cores are available in Xilinx's ISE Design Suite 13.3 and can be evalauated free of charge.

For more information visit: www.xilinx.com