Date: 29/09/2011

ST-Ericsson designed its 40-nm mobile SoC using Cadence Virtuosa and Encounter

ST-Ericsson has developed 40-nm mobile SoCs using Cadence EDA tools Virtuoso and Encounter. Cadence claims that ST-Ericsson has achieved a 10x productivity gain by using the Cadence tools.

"The result from ST-Ericsson demonstrates that the enhancements and improvements we have implemented deliver a truly unified mixed-signal flow and help our customers master today's complex mixed-signal designs both predictably and efficiently," said Qi Wang, group director, Solutions Marketing at Cadence. "Our mixed-signal solution embodies the tenet of the EDA360 vision and delivers on our end-to-end approach to Silicon Realization."

"Using the Cadence mixed-signal solution enabled us to accelerate our design time by 10x compared with the design of a previous chip built in 65 nanometers," said Rolf Becker, development manager at STE. "We saw significant advantages resulting from our use, for the first time, of OpenAccess as the single database. Any design change that was done by one designer was immediately visible to the rest of the global design team without doing lengthy stream-out/stream-in operations, and we were amazed how much time was saved."

The release states OpenAccess, the industry standard database, helped boost productivity during the implementation phase by enabling a seamless collaboration and data transfer between the analog and digital design teams. ST-Ericsson also used Cadence QRC Extraction, a parasitic extraction technology for analog device-level and mixed-signal interconnect extraction, and the Cadence Encounter Digital Implementation System for RTL-to-GDSII implementation.