Date: 16/08/2011

Sunplus picks Cadence' transaction-level modeling flow for IC design

Cadence Design Systems, Inc.has announced that Sunplus Technology Co., Ltd has adopted the its transaction-level modeling (TLM) flow with Cadence C-to-Silicon Compiler for its next-generation multimedia system-on-chip (SoC) design.

By deploying transaction-level modeling with Cadence C-to-Silicon Compiler, which delivers high-level synthesis, Sunplus engineers can design and verify their chips at a higher level of abstraction, and this enables them to explore more architectural options and more quickly re-target IP to satisfy various performance, power consumption, and cost needs, says Cadence.

"In order to accelerate system development time, we decided to adopt the Cadence C-to-Silicon Compiler for our next product because it can generate the best quality of results," said Cheng-Yuh Wu, director of DVD IC Design Division I at Sunplus. "In addition, C-to-Silicon Compiler, as part of a TLM flow, helps our engineering teams optimize their designs early in the design cycle, including power characteristics. Perhaps most important, we can use a more abstract language-SystemC-than traditional Verilog/VHDL to do our design. This translates into shorter development time for complex designs, with higher IP reuse for subsequent end products."

"TLM design and verification continues to grow in importance and industry use as time-to-market pressures mount in the highly competitive consumer electronics markets," said Jack Erickson, director, product marketing, System Realization at Cadence. "The Cadence TLM flow with the C-to-Silicon Compiler is currently helping many leading semiconductor and system companies, including Sunplus, tackle the challenges of today's complex system designs. This open, connected, and scalable approach to system realization delivers significantly faster turnaround time for the development and re-use of complex designs -and delivers on the EDA360 vision."