Date: 13/04/2011

Cadence DDR4 IP offerings: PHY IP; controller IP; memory models; verification IP; tools and methodologies

Cadence Design Systems, Inc. has announced DDR4 IP cores for complex semiconductor designs such as SoC design. Cadence gains IP offering strength after recently acquiring Denali. The VLSI IP core offering includes hard and soft PHY IP; controller IP; memory models; verification IP; tools and methodologies; and signal integrity reference designs for the package and board.

"Memory management IP is central to successfully delivering differentiated products, and the quality of the IP dramatically impacts the performance, power and signal integrity of the entire SoC and system," said Vishal Kapoor, vice president of the SoC Realization Group for Cadence. "Many designers are finding it increasingly challenging to design and integrate memory management IP onto their SoCs. As the only company to support its high quality IP with an integration environment spanning every aspect of design - from silicon to package to board - we dramatically lower the risk associated with realizing complex DDR4-based SoC designs."

The DDR4 specification, an evolutionary SDRAM memory technology standard currently under review at JEDEC, proposes speeds ranging from 1600 mega transfers per second (MT/s) up to 3200 MT/s, more than 50 percent faster than the current DDR3 standard. As the standard evolves to support higher frequencies and throughput, signal integrity, power and performance issues multiply. Successful IP integration hinges on both the quality of the IP and the sophistication of the integration environment.

Cadence says its soft PHY and controller provide tremendous flexibility and can be synthesized to support the full range of frequencies and voltages. Designers can deliver either a pure DDR4 SoC, or combine DDR4 with other technologies like DDR3 or LPDDR2. The specification is expected to be finalized this year.

"We expect vendors, especially in the networking and enterprise markets, to begin designing equipment utilizing DDR4 in 2012," said Ganesh Ramamoorthy, principal research analyst, Gartner. "Since SoC design start well in advance of system design, we believe the demand for DDR4 IP will begin from now on and grow strongly to reach peak demand by 2014."

Availability:
DDR4 controller IP, verification IP and memory models are available now, and supported by both Cadence and third party design tools and methodologies. A soft DDR4 PHY is expected to be available this quarter, while a hard PHY solution for 28-nm TSMC geometries is expected to be available by Q3 2011.