Date: 03/04/2011
Smart power semiconductor tech from ST to reduce power consumption
ST Microelectronics announced that it has successfully demonstrated smart power semiconductor technology developed to reduce power consumption in wide range of electronic systems - from new medical equipment to battery chargers in hybrid electric vehicles.
ST said it has already verified the feasibility of this new semiconductor technology by producing, in cooperation with a world-leading medical equipment supplier, a demonstrator chip for ultrasound scanners that can handle over one hundred channels, to address the next generation of scanners that will require thousands of channels. The best technology available today on the market does not allow this level of integration, with current chips typically handling only eight channels, claims ST.
The development of the technology is one of the results of an advanced European R&D project. In Europe, the EU has stimulated much research and development work in this field through the ENIAC (European Nanoelectronics Initiative Advisory Council) initiative. Within the ENIAC framework, ST and 17 other European partners have formed the SmartPM (Smart Power Management in Home and Health) consortium to answer this growing need for energy efficiency. The SmartPM consortium includes companies and academic institutions from nine countries: Belgium, France, Germany, Ireland, Italy, the Netherlands, Norway, Spain and Sweden. The SmartPM partners are working together to develop innovative semiconductor technologies, circuit designs and system architectures.
"Semiconductor technologies that can drastically reduce electrical energy consumption in consumer and industrial appliances have existed in the labs for many years and their potential contribution to the reduction of worldwide power consumption is significant," said Claudio Diazzi, Group Vice-President, Technology R&D, STMicroelectronics. "However, the cost of these technologies has previously been too high to make them commercially viable. We believe that this new smart power technology will make a significant difference."
About the Technology: The new technology is a next-generation variation of ST's world-leading BCD (Bipolar-CMOS-DMOS) smart power semiconductor technology that combines SOI (Silicon-on-Insulator) substrate technology with 0.16-micron lithography. This will enable chip designers to combine high-density logic circuitry (1.8V and 3.3V CMOS) with full dielectric isolation and a component portfolio including power MOSFET transistors that can operate up to 300V, low noise devices, and high-value resistors, leading to ASICs that cannot be implemented using conventional bulk-silicon substrates.
About SmartPM: The SmartPM partners receive partial R&D funding from the ENIAC Joint Undertaking and from various national programs/funding authorities: the German Federal Ministry of Education and Research (BMBF); the Belgian IWT; the French Ministère de l'Economie, des Finances et de l'Industrie; Secrétariat d'Etat à l'Industrie (STSI); Enterprise Ireland; the Italian Ministero Istruzione Università Ricerca; APRE (Agenzia per la Promozione della Ricerca Europea); the Dutch SenterNovem; the Research Council of Norway; the Spanish DGI-Ministerio de Educación y Ciencia; and the Swedish Vinnova.