Date: 13/03/2011

Xilinx updates its FPGA software 'ISE design suite' to support 7 series

Xilinx has made available its updated version of FPGA design software tool ISE Design Suite ISE13. This updated version speeds up the FPGA design and also supports Xilinx latest devices the 7 series FPGAs, including 2-million-logic-cell Virtex-7 2000T device, fabricated by stacking multiple dies of FPGA chips.

ISE Design Suite 13 speeds up verification and allows Plug-and-play IP with IP-XACT Support and allows multiple engineers working in parallel from different places.


The ISE Design Suite 13' new hardware Co-Simulation capability and AMBA4 AXI4 (Advanced Extensible Interface) bus functional simulation models helps design engineers in productivity gains.

Through real-time simulation, verification engineers can test implemented blocks of the design while leaving other blocks that are still under development in the simulator accelerating overall verification by up to 100 times faster than native simulation.

The new optional AXI4 bus functional model can also be added to verification test benches to drive stimulus and to validate interconnect logic of customer supplied IP.

The team design flow provides additional functionality and allows early implementation results on completed portions of the design to be locked down without having to wait for the rest of the design team. This new capability supports advanced optimizations including intelligent clock gating that can provide up to 30 percent dynamic power reduction, facilitates faster timing closure and timing preservation for the remainder of the design.

The new ISE Design Suite 13 suite now delivers new open standards by supporting development with both Xilinx and third party IP. New in this release is a configuration option to the AXI interconnect that allows a 50 percent reduction in the interconnect silicon footprint using sparsely connected AXI4 interconnect. For high performance AXI4 systems, customers can get up to 20 percent higher system bandwidth for interconnect and memory interfaces, says Xilinx.

Also provided is a new IP-XACT based IP Packager for Xilinx Alliance Program Members. IP-XACT based IP Packager from Xilinx enables an Alliance Member to package their IP so that it can be easily accessed out of the CORE Generator IP repository. IP-XACT enables a consistent user experience for using IP from both Xilinx and its Alliance Program Members. In ISE Design Suite 13, 50 Xilinx IP cores support IP-XACT and within a year, all Xilinx IP cores will support IP-XACT. Future releases will open this same capability to customers for easy design reuse of their IP.

To make it easier for users to simulate encrypted IP, Xilinx says it is the first company to offer an IEEE P1735 compliant simulation model for the AXI BFMs supporting AXI3 or AXI4 protocol for simulation interoperability with major third party simulators. A fully functional IEEE P1735 encryption flow for Alliance Program Members will be available later this year.

For applications such as wireless baseband, video and beam forming that require linear algebra mathematics to be implemented a new highly configurable Linear Algebra LogiCORE IP core is now available inside CORE Generator. The IP core implements matrix operations, such as: matrix addition, subtraction, multiplication, and matrix-scalar multiplication.

Additional processing support for embedded systems design in ISE 13 is delivered with a new high assurance MicroBlaze processor. In systems that require redundancy and fault detection, the high assurance MicroBlaze processor provides memory protection and the capability to have redundant MicroBlaze processors with lockstep for meeting high assurance and reliability requirements. By providing the processor and comparator logic in an integrated easy to use IP block, designers can securely design the soft-core MicroBlaze processor into secure applications such as ATMs that frequently require error detection.

Availability: Now
Price: US$2,995 for the Logic Edition and now supports 32- and 64- bit Windows 7. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site. For details visit www.xilinx.com/tools/designtools.htm.