Date: 07/03/2011

Synopsys introduces a tool to check chip designs for litho bugs

Synopsys, Inc. has introduced Proteus LRC for lithography verification. Proteus LRC helps in identifying locations in a design that are sensitive to process variations so that the chips can be made bug free at design stage itself. Proteus LRC is integrated into the Proteus Mask Synthesis flow and is targeted for use by OPC and mask data preparation groups at semiconductor manufacturers like Micron Technology, Inc.

Proteus LRC supports the nodes 28-nanometer (nm) and below technology by using industry-proven optical proximity correction (OPC) models and rigorous first-principle models from embedded Sentaurus Lithography technology. It is imperative for lithography rule check (LRC) tools to accurately predict and verify the critical dimension (CD) variation through the process window to help ensure that adequate process margins are maintained for optimum wafer yield. The Sentaurus Lithography technology embedded in Proteus LRC allows easy access to rigorous first-principle models for resist profiles and topography effects when identifying at-risk hotspots and determining the appropriate course of action.

This tool supports latest manufacturing techniques like extreme ultraviolet lithography (EUV) and double-patterning technology (DPT), by taking advantage of Synopsys' Proteus Pipeline Technology, Proteus LRC is able to efficiently handle the full-chip layout requirements of EUV.

Synopsys says Proteus LRC has been fully integrated in the Proteus Mask Synthesis flow with near-linear scalability to hundreds of standard x86 processor cores, allowing full control over turn-around time and delivering the lowest cost of ownership.