Date: 01/02/2011

Arasan develops the Universal Flash Storage (UFS) memory IP core

Arasan Chip Systems, Inc. has announced it has been developing the Universal Flash Storage (UFS) IP core.

The UFS standard is based on modular layered protocol architecture. This architecture enables an efficient interface implementation with the ability to scale the interface to meet future performance requirements. Arasan said with its domain expertise and involvement with the JEDEC body has been developing a complete IP core solution for UFS - spanning Software, Controller IP, MIPI UniPro Link, and M-PHY IP.

"Implementing a complex memory interface such as UFS requires an in-depth understanding of the UFS specification and architecture," said Prakash Kamath, Vice President of Engineering at Arasan. "Customers can rely on our UFS IP core, backed by the confidence in our expertise, to hasten introduction of their SoC's."

"SoC designers are looking for a common non-volatile memory interface that can support different system architectures while ensuring they have a wide supply of memory chips," added Kamath. "Arasan is committed to keeping our UFS IP in synch with the evolving JEDEC standard, which is scheduled to get ratified in the first half of 2011."

Arasan has also announced the appointment of Mike Kliment, as the Director of Analog and Mixed Signal.