Date: 17/01/2011

ARM Cortex-M0 processor based MCU and CAN Transceiver in single chip

NXP Semiconductors has announced the availability of new SiP device packing both ARM Cortex-M0 processor based MCU and high-speed CAN Physical Layer transceiver. These System in Package (SiP) devices LPC11C22 and LPC11C24 offer CAN functionality in low-cost LQFP48 package.

The SiP device is aimed at cutting the additional cost involved in external CAN transceiver in industrial and automation applications for factories, buildings and in the home. NXP says Integrating the CAN transceiver on board increases system reliability and quality, reduces electrical interconnect and compatibility issues, and reduces board space by over 50 percent while adding less than 20 percent to the MCU cost. The LPC11C22 and LPC11C24 are the latest additions to the LPC11C00 series of CAN 2.0B-compliant controllers.

"Offering a highly optimized CAN solution in a single package simplifies industrial network design," said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. "The close coupling of transceiver and 32-bit MCU with CANopen protocol support directly on-chip extends our plug-and-play system approach."


LPC11C22/C24 CAN Physical Layer is designed for up to 1 Mbit/s High-Speed CAN networks with Electrostatic Discharge (ESD) protection, improved Electromagnetic Compatibility (EMC) and low power operation, high DC handling capability on CAN pins, Transmit Data dominant time-out function, undervoltage detection, and thermal protection features. The LPC11C22/C24 CAN Physical Layer is fully compliant with the ISO 11898-2 standard for two-wire balanced signaling and is optimized for sensor applications and rugged industrial CAN networks.

CANopen drivers and APIs are provided in on-chip ROM to ease the design of embedded networking applications based on the CANopen standard such as machines and elevators. The following functions are included in the API:
CAN set-up and initialization
CAN send and receive messages
CAN status
CANopen Object Dictionary
CANopen SDO expedited communication
CANopen SDO segmented communication primitives
CANopen SDO fall-back handler


NXP claims 45 DMIPS capable LPC11C22 and C24 require 40-50 percent smaller code size than 8/16 bit microcontrollers for most common microcontroller tasks due to the use of ARM Cortex-M0 v6-M instruction set, which is built on a fundamental base of 16-bit Thumb instructions unique to 32-bit microcontrollers today.

Other key features of the LPC11C22 and LPC11C24 include:
32KB/16KB Flash, 8KB SRAM
32 Vectored Interrupts; 4 priority levels; Dedicated Interrupts on up to 13 GPIOs
CAN 2.0 B C_CAN controller with on-chip CANopen drivers, integrated transceiver
UART, 2 SPI & I2C (FM+)
Two 16-bit and two 32-bit timers with PWM/Match/Capture and one 24-bit system timer
12MHz Internal RC Oscillator with 1% accuracy over temperature and voltage
Power-On-Reset (POR); Multi-level Brown-Out-Detect (BOD); 10-50 MHz Phase-Locked Loop (PLL)
8-channel high precision 10-bit ADC with ±1LSB DNL
36 fast 5V tolerant GPIO pins, high drive (20 mA) on select pins
High ESD performance: 8kV (Transceiver) / 6.5kV (Microcontroller)
Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI) CAN transceiver

Editorial Product Rating: ** (Average Plus)