Date: 06/12/2010

Magma's new version of Talus with 5x faster turn around time for designing 20nm range SoCs

Magma Design Automation has unveiled Talus 1.2, the new updated chip design EDA software. Magma says this new version enables LSI designers to implement 1 million to 1.5 million cells per day on large designs or blocks of 2 million to 5 million cells - with crosstalk avoidance, advanced on-chip variation (AOCV) and multi-mode multi-corner (MMMC) analysis enabled. Already silicon-proven at the 40-nanometer (nm) node, Talus is currently in use for complex 28-nm designs. With these latest enhancements, Talus is primed to handle the challenges of designing at the 20-nm process node and beyond, claims Magma.

The highlights of this product as said by Magma include:
Talus 1.2 deliver 5x faster turnaround time, including:
Talus MX Router: Offers enhanced global, track and detailed routing capabilities, convergent timing through the flow, and eliminates DRC violations.
Talus MX Timer: Based on Magma's next-generation sign-off timing analysis technology, enables faster more accurate timing analysis.
Talus MX Extractor: Based on Magma's latest high-speed, multi-corner extraction technology provides faster, more accurate extraction.
Concurrent MMMC optimization: Manages five times as many timing scenarios than traditional solutions, while providing a 10X runtime improvement.
AOCV: Ensures tight timing correlation throughout the flow.
Crosstalk Avoidance: Detects and corrects crosstalk violations during optimization and implementation.

"The positive results we achieved from Magma's Talus 1.2 platform reaffirmed our decision to select this tool to support our complex silicon project needs," said Mr. George Apostol, executive Vice President of Engineering and Operations, and chief technical officer at Exar Corporation. "Critical to our customers, our devices must support high levels of data traffic without bottlenecks, requiring efficient routing. Talus 1.2 has solved many physical design issues and has improved place and route runtimes over prior releases, enabling us to shorten development cycles and accelerate shipping next-generation devices to customers to meet dynamic market requirements."

"Chip design teams are under constantly increasing pressure to improve productivity, even as the designs they tackle grow in size and complexity," said Mr. Premal Buch, General Manager of Magma's Design Implementation Business Unit. "Economics dictate that design teams cannot expand in proportion with growing design sizes, nor can turnaround times lengthen. To improve productivity, tools must provide more capacity and faster turnaround times while enabling designers to squeeze out more performance and reduce power consumption in their SoCs. Talus 1.2 does just that. It delivers the fastest turnaround times, highest capacity, and best quality of results for the next generation of IC designs at the 28-nm process node and below."

Magma claims a networking company was able to implement a 40-nm, 2-million-instance design with 10 sign-off scenarios in just 2 days with full CCS, MMMC and crosstalk analysis enabled.

Magma has also unveiled Talus Vortex FX, a three times faster place and route EDA software compared the above mentioned Talus 1.2. SoC class semiconductor chip designers can generate 2 million to 5 million cells per day with crosstalk avoidance on the same computer server running any previous version of place and route, claims Magma.

Talus Vortex FX catapults Magma's place-and-route technology far beyond anything else out there," said Mr. Rajeev Madhavan, Magma Chief Executive Officer. "Our engineering investment in the Distributed Smart Sync technology has yielded great benefits for our customers. It puts Magma in the unique position of enabling designers to accelerate the development cycle of more complex and differentiated products without lengthening design cycles, increasing hardware costs or adding resources. This is critically important for customers adopting 28-nanometer (nm) processes and looking forward to 20 nm."

Magma names two of its customers who could design semiconductor chips using Magma's EDA tools. Soft modem chipset developer Icera Inc. has developed of Icera's 28-nanometer (nm) SoC design flow for its next-generation chipsets using Magma's Magma's Talus platform.
"To maintain technical leadership in the cellular modem business, Icera cannot afford to compromise on performance, power consumption or area efficiency," said Mr. Peter Hughes, Vice President of Silicon Engineering and Operations at Icera. "The advanced technology and tight integration of the Talus platform enable Icera to meet our stringent power and area targets and to reduce time to market for our next-generation 28-nm soft modem chipset."

Another customer Melfas who is into developing capacitive-sensing touch input solutions has used the Magma's Talus platform, including Talus RTL, Talus Vortex and Talus Power Pro, and the FineSim SPICE circuit simulation tool to implement two of its next-generation MCS-8000 touch sensor semiconductor chips, which feature ARM Cortex processors. The Melfas ICs are used to interface LCD touch panels in mobile phones, smartphones, MP3 players, monitors and other consumer electronics.

"Our customers demand low-cost turnkey touch screen module solutions that provide advanced functionality without increased power consumption," said Mr. Dongjin Min, Chief Technical Officer of Melfas. He added, "The Magma software provides the capabilities we need to reduce turnaround time, area and power of our mixed-signal SoCs. The reference flow and Magma tools' proven ability to streamline integration of ARM Cortex-M series processors into complex designs gave us greater confidence in achieving silicon success."

Editorial product rating of Talus 1.2 and Vortex FX: ** (Average Plus)