Date: 29/11/2010

Clock buffer families from TI with additive jitter of less than 100 fs RMS

Texas Instruments Incorporated (TI) has released three separate clock buffer families: the CDCLVC11xx, CDCLVD12xx/21xx and CDCLVP12xx/21xx. These buffers are targeted at a variety of communication applications with frequency support of up to 2GHz (LVPECL), 800MHz (LVDS) and 250MHz (LVCMOS). These devices are rated to meet stringent additive jitter requirements for wireless infrastructure, data communications and telecommunications, medical imaging and industrial applications.

Key features and specs of LVCMOS, LVDS and LVPECL clock buffer families

1) CDCLVC11xx clock buffer family for LVCMOS output
Generate 2, 3, 4, 6, 8, 10 and 12 copies of LVCMOS clock outputs from a single LVCMOS input.
Additive jitter of less than 100 fs RMS (12 kHz - 20 MHz).
Low output skew of 50 ps.

2) CDCLVD12xx/21xx clock buffer family for LVDS output
Generates 4, 8, 12 or 16 copies of LVDS clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs.
Additive jitter of less than 300 fs RMS (10 kHz - 20 MHz).
Low output skew of 20 ps.
Universal input support eliminates the need for additional external discretes for signal level translation.
Small package options in QFN-16/28/40/48 saves board space by up to 600 percent compared to competitive devices.

3) CDCLVP12xx/21xx clock buffer family for LVPECL output
Generates 4, 8, 12 or 16 copies of LVPECL clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs.
Additive jitter of less than 100 fs RMS (10 kHz - 20 MHz).
Low output skew of 15/20/25/30 ps.
Universal input support eliminates the need for additional external discretes for signal level translation.
Small package options in QFN-16/28/40/48 saves board area by up to 600 percent compared to competitive devices.

Price:
CDCLVC11xx: Each US$0.90 for 1K pieces.
CDCLVD12xx/21xx: Each US$2.85 for 1K pieces.
CDCLVP12xx/21xx: Each US$3.30 for 1K pieces.

Availability: Now