Date: 14/09/2010

1GHz DSP core from CEVA

CEVA has released the CEVA-X1643, a 1GHz DSP core. This DSP core is designed to boost overall chip performance for a broad range of applications such as wireline and wireless communications, surveillance, portable multimedia and more. The CEVA-X1643 is built using the CEVA-X DSP architecture.

The CEVA-X1643 provides support for an advanced data cache and tightly coupled memory architecture. This DSP core also provides memory management support to simplify RTOS and multi-tasking. The CEVA-X1643 has an integrated Power Scaling Unit (PSU), Configurable 64/128 bit AXI system busses supporting high memory bandwidth. The CEVA-X1643 has inherent support for migration from TI C6x C-code. This DSP core is fully compatible with all CEVA-X family of products.

"The CEVA-X1643 is an impressive addition to the CEVA family of DSP cores, offering 1 GHz DSP performance and excellent energy efficiency," said Will Strauss, founder and president of Forward Concepts. "The addition of the data cache memory architecture and power scaling unit to the CEVA-X architecture, while leveraging the CEVA-X industry renowned development tools, should prove appealing to a broad range of semiconductor companies looking for a high-performance DSP core that can efficiently support their legacy code with minimal effort."

"Building on our highly successful CEVA-X family of DSPs, the CEVA-X1643 offers a new level of performance to enable vendors using standard DSP-based chips and ASSPs to move to more flexible and cost-effective core-based SoC designs," said Eran Briman, VP of marketing at CEVA. "The DSP's advanced data cache architecture and software development environment dramatically simplifies the migration of legacy code to the CEVA-X architecture, enabling true, all-in-C programming of the CEVA-X1643."

The CEVA-X1643 DSP features a Very Long Instruction Word (VLIW) architecture combined with Single Instruction Multiple Data (SIMD) capabilities. Its 32-bit programming model supports a high degree of parallelism, including the ability to process up to eight instructions per cycle, and 16 SIMD operations per cycle.

The CEVA-X1643 is equipped with an Advanced eXtensible Interface (AXI) based memory sub-system supporting; configurable AXI bus width, parallel read and write transactions, read after write transactions and other advanced capabilities, ensuring target performance is met in a real-life system. The use of de-facto industry standard system buses together with a fully cached CEVA-X processor enables high performance, shorter design cycle and easy integration into the target SoC.

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