Date: 27/08/2010

New UHS-II PHY IP core from Arasan chip

Semiconductor IP vendor Arasan has released a UHS-II PHY IP core, a memory interface being finalized by the SD Association. This core can be used in SD host, device as well as other SDIO configurations.

The SD 3.0 specification defines cards with a maximum memory capacity of 2TB and interface bandwidth that scales up to 104MBps in UHS-I. SD Association has defined a new standard - UHS-II. UHS-II delivering for non-volatile memory interface achieving peak interface speeds of 3.12 Gbps in Full duplex mode and 1.56 Gbps in Half duplex mode. These speeds targets gaming and multimedia applications.

Arasan offers a Total IP Solution for this PHY IP core consisting of behavioral model, timing model, GDS II database, LEF model and a LVS netlist.

"Implementing the UHS-II interface in an advanced SoC process node requires in-depth understanding of high-speed design and complex mixed-signal interactions," said Prakash Kamath, Vice President of Engineering at Arasan. "With this release, we are the only company with an end-to-end SD IP solution covering UHS-II controller, PHY and corresponding software stacks."

"To keep pace with the increasing demand for high-performance non-volatile memory interface, Arasan has achieved yet another first - with its high-performance UHS-II PHY IP core," said Somnath Viswanath, Director of Marketing at Arasan. "SoC designers integrating this new standard benefit from our leading edge SD IP cores and Mixed Signal expertise to achieve first silicon success."

For more information visit: www.arasan.com