Date: 09/06/2009

PCI Expess 3.0 PHY IP core for SoC designs in 40nm process

Gennum's Snowbush IP group has made available integrated PCI Express 3.0 (Gen 3) PHY and Controller IP core for SoC designers to enable their 40nm process node based chips with PCIe 3.0 speeds of 8GT/s. This PIC-SIG standard compliant IP cores has proprietary 5-tap Decision Feedback Equalization (DFE) and H-bridge transmit driver. DFE is high performance non-linear equalizer, which can handle spectral nulls where as H-bridge transmit driver cuts the power consumption.

This IP core holds on-chip VLSI functional blocks such as I/Os, Electro-Static Discharge (ESD) protection structures, and Physical Coding Sub-layer (PCS) Layer in 1-, 2-, 3-, and 4-lane configurations. Each lane of the PHY can be configured to operate in Gen 1, Gen 2, or Gen 3 mode. Multiple 4-lane PHYs can be configured as x8, x16, x32, and greater links. An on-chip Fractional-N Phase Locked Loop (PLL) Frequency Synthesizer with integrated Spread Spectrum Clocking is used for simplified external clocking and reduced SoC complexity.

The Controller with micro and macro power option features low latency-pipelined architecture for a higher throughput. Available as an Endpoint, Root, Dual Mode, and Switch for x1, x4, x8, and x16 lane configurations the digital controller can be targeted for many applications of PCI Express.

Some more highlights include:
A proprietary dual-loop hybrid clock-and-data recovery (CDR) architecture which recovers the clock with less jitter
A coupled ring oscillator VCO design with better jitter performance
Internal voltage and current regulation for sensitive circuits
Fully differential circuitry and clock signaling
Extensive use of guard rings within the macro
Atomic Operation (FetchAdd, Swap, Compare and Swap (CAS))
Address translation services
Transaction-Layer Processing Hints (TPH)
5.0 GT/s and 8.0 GT/s speed negotiation
Optional and Mandatory Power Management Features

Comments from Gennum's executive:
"PCIe 3.0 IP is critical for the development of next-generation computing products. Our momentum in high-speed IP is unquestionable with our recent SATA 6.0 Gb/s IP release, and now our customers can license our 8 GT/s PCIExpress IP. Snowbush IP again demonstrates it consistently delivers siliconproven cores at the leading edge of another emerging market, enabling many high-profile semiconductor suppliers and OEMs to get to market first," said Ewald Liess, General Manager of the Snowbush IP group for Gennum. "Our customers rely on our extensive experience at data rates of 5 Gb/s and above-high-speed serial interface IP that is high yielding and optimized for the performance, power, size, and cost of our customers' target applications. They know and see the value of outsourcing these complex IP blocks."

Analyst Comments:
"PCI Express 3.0 doubles the effective throughput of the existing 2.0 standard, meeting many of the future throughput needs of interface chips for servers, communications, and enterprise storage devices," said Jag Bolaria, senior analyst at the Linley Group. "We anticipate that this new standard will begin to see deployment in 2010. Snowbush now has both the PHY and Controller, allowing PCIe 3.0 market movers a cost-effective way to deploy products based on this standard."

PLX Technology has licensed this core to use in its PCIe switches.
Comments from PLX executive:
David Raun, Vice-President of Marketing and Business Development at PLX Technology said, "We did a complete technical and business evaluation of all vendors and chose he Snowbush IP PCIe 3.0 PHY because it has the highest performance, lowest power and is the most robust solution. By licensing the Snowbush PCI Express 3.0 PHY, we will dramatically reduce development time and continue to provide superior, feature-rich PCI Express switches."