Date: 13/05/2009

Synopsys Launches in-design verification tool to cut chip-design time

Synopsys has released IC validation tool to take care of physical verification of the semiconductor IC chip during design-stage itself for nodes at and below 45nm.

The highlights of this VLSI EDA tool with simplified user interface are,

The software is scalable to different computing hardware platform on which it is installed so that the muIti-core computing systems power is well utilized.
Eliminate the design changes and correction loops running between semiconductor-fab engineers and VLSI engineers.
Reduce design time through in-design verification, incremental processing, and automatic error detection and correction.

Here is what the semiconductor fab expert says,
"TSMC employs rigorous qualification criteria to help ensure DRC/LVS accuracy for signoff physical verification. We have worked closely with Synopsys during the development of IC Validator and have included it in our 28nm EDA qualification program," said S.T. Juang, senior director of design infrastructure marketing at TSMC. "Such a collaboration with Synopsys has produced good results with IC Validator in TSMC's most current physical verification EDA qualification report."

Synopsys has said in its other press release, NVIDIA has purchased this IC Validator physical verification solution.