Date: 20/04/2009

ARM delivers physical IP libraries tuned to TSMC's 40 nm process

ARM released physical IP platform for TSMC's 40nm G manufacturing process for feature packed SoC class semiconductor devices for consumer electronics applications. Chip designers who are migrating their design to 40nm for the benefits of low power and added features can use this IP library to save their time in checking fab related bugs in their designs.

This fab-ready IP is supported by Synopsys for speedy implementation of physical IP in their newly released chip design software Lynx. The kind of consumer applications benefited by semiconductor devices designed using these IP libraries includes disc drives, STBs, mobile phones, networking applications, HDTV, and gaming and graphic applications.

The 40 nm physical IP platform offer includes standard cell libraries, power management kit and ECO kit library extensions. This platform comes with memory compilers, which include SRAM, Register File, and ROM compilers.

The Interface IP offered in this platform covers general purpose I/Os, specialty I/Os and DDR memory interface macros to connect ARM processor to the outside world. This Interface IP incorporates several power and leakage saving modes that can be dynamically controlled to further optimize overall SoC power. ARM also offers full speed DDR PHY solutions with at speed BIST and DFI support for flexible memory controller integration along with specialty I/O such as LVDS physical interface.

"ARM is in the unique position of developing processor IP and physical IP in parallel so they fully complement each other and reduce the overall design cycle" said Simon Segars, executive vice president and general manager, physical IP division, ARM. "We further enhance our technology through early engagement with the leading foundries and EDA companies to ensure a robust support infrastructure exists, providing the designer with a low risk, silicon proven, cost efficient design strategy. Through our strategic relationship with TSMC we can optimize the physical design with the manufacturing process technology to provide optimal results."

"ARM and Synopsys are dedicated to reducing design cycle challenges through close collaboration on foundry-ready physical IP platforms and integrated design tools," said John Chilton, senior vice president of marketing and strategic development, Synopsys. "ARM offers designers a comprehensive 40 nanometer offering, and we have been working with ARM to ensure the new platform is validated with our Lynx Design System. Pre-testing ARM IP with Lynx's Foundry-Ready System provides a low-risk path to a proven, manufacturing-ready SoC solution at 40 nanometer. The combination will deliver highly optimized designs with accelerated, reduced-cost chip implementations."

The 40nm G libraries are available at http://designstart.arm.com/.