Date: 15/04/2009

DesignWare IP from synopsys for AMBA 3 AXI supports hybrid bus architecture

The new enhanced DesignWare IP from Synopsys for ARM AMBA 3 AXI with hybrid bus architecture implementation saves few SoC chip resources. Through this hybrid architecture, the processor core and peripherals can communicate either by a dedicated high-performance or a shared low-performance channels to be combined within a single AMBA 3 AXI on-chip interconnect. This new architecture requires lesser logic blocks resulting in reduced physical area on the chip, drop in power consumption, and fall in the routing congestion. The hybrid architecture is ideal for system-on-chip (SoC) designs that use a native AMBA 3 AXI interconnect. It also reduces the area impact for SoC designs moving from an AMBA 2.0 AHB to an AMBA 3 AXI-based architecture.

The new hybrid architecture offers option to the designers to chose either a shared or dedicated bus within a single AMBA 3 AXI on-chip bus interconnect to connect the master and slave functions in the chip. The key advantage of this architecture is reduction in number of dedicated buses and wires in the system, also this architecture eases timing closure by allowing for greater control of the critical paths throughout the bus interconnect.

In a recent case study using the Galaxy Implementation Platform, Synopsys configured the DesignWare IP for AMBA 3 AXI interconnect fabric consisting of 10 master and 10 slave ports. The hybrid architecture allows the low bandwidth master-slave links of the dedicated bus to be replaced with a shared bus, while keeping the high-bandwidth master-slave links as dedicated buses. With this implementation, Synopsys was able to reduce the number of wires by 52 percent, area by 30 percent, and power consumption by 30 percent when compared with Synopsys' traditional DesignWare IP for the AMBA 3 AXI interconnect fabric without the hybrid architecture.


The hybrid architecture in the DesignWare IP for the AMBA 3 AXI interconnect is available now to early adopters. The IP is provided in synthesizable source RTL. General availability is scheduled for Q3 2009.