Date: 25/03/2009

Lynx from Synopsys to speed up the chip design

From micron geometries in 90s to sub nano chip fabrication geometries now, VLSI design engineers have treaded a path with full of surprise issues and new challenges. The issues, which were not even imagined by VLSI design engineers a few years back such as post-silicon bugs is a major challenge at present nano meter (nm) nodes. The EDA vendors have continuously redesigning and launching new products to take care of VLSI design issues. Whenever they are not up to the speed of market requirements their sales dropped otherwise when their sales dropped they turned into more innovative. 2009 is one such year where the pressure from semiconductor market to innovate is more than previous years.

In that sense, here comes a new chip design environment called Lynx Design System from Synopsys. Low power, fast design turn around time, and low design cost are the highlighted benefits of this VLSI design tool.


The four core components of this chip design EDA tool and the features of these components are,

1. Full-chip Production Flow from RTL to GDSII:
Supports 65 and 40 nanometer (nm) nodes
The low power techniques include multi-corner multi-mode (MCMM), state-retention power gating (SRPG) and dynamic voltage frequency scaling (DVFS)
Best design practices from the ARM-Synopsys implementation Reference Methodologies (iRM) using ARM physical IP optimized for ARM processors are embedded.

2. Foundry-Ready System
Pre-validating technology files and libraries for use in the flow.
Hard IP checker to validate incoming IP by performing standalone and interoperability testing with other design IP for faster implementation.
Process-specific checks and representative default settings for factors that impact manufacturability such as metal fill density and on-chip timing variation.

3. Runtime Manager
This component helps to manage the productivity of design team by providing the GUI interface to setup and validate the design flow variables and easy interface to create and modify the flow. From the Runtime Manager, designers can monitor one or more design blocks concurrently as they progress through the design flow, with dashboard reporting of status at each design step and to debug the problems in the
context of the flow.

4. Management Cockpit:
Help to predict the project completion time and to plan and manage the resources to speed up the design. Management Cockpit displays current design status against specified goals. Design parameters such as timing, utilization, clock skew, leakage power, and fault coverage and system resources such as run time, CPU and memory usage are tracked at the block and chip level, and users can add their own metrics to the flow.

Here is a quote from wikipedia on post silicon validation, "The industry today is focused on techniques that allow designers to better amortize their investment in pre-silicon verification to post-silicon validation."

When semiconductor companies spend millions on SoC class chip development, the selection of right EDA tools matter a lot in ensuring design success.