Date: 18/03/2009

MIPS offers USB-IF certified USB 2.0 PHY IP core

MIPS Technologies' 40nm USB 2.0 High-Speed PHY silicon IP core is certified from the USB Implementers Forum (USB-IF) to ensure interoperability with other USB 2.0 devices. This semiconductor IP Core also meets TSMC's TSMC9000 standards in its 40nm LP process.

The physical area of this IP functional block on silicon chip is below 0.6mm2 and consumes a power of less than 80mW. Advanced programmability feature allows VLSI designers to fine-tune their system's analog parameters.

"SoC developers are moving to advanced technology nodes to reduce costs for many high-volume mobile and consumer devices, and they need a high-quality, reliable and interoperable USB solution," said Celio Albuquerque, director of Physical Connectivity Solutions, Analog Business Group, MIPS Technologies. "Following our recent announcement of the industry's first 40nm USB PHY IP and first USB-certified 1.8v 45nm USB PHY IP, we are pleased to announce these new milestones. As a TSMC partner, we are committed to offering early access to proven IP in the most advanced nodes, helping customers get to market quickly at the lowest cost and fastest time to integration."