Date: 11/03/2009

USB 2.0 and PCI Express IP cores compliant with 65 nm process technologies

Synopsys has announced that its DesignWare USB 2.0 nanoPHY IP and PCI Express 1.1 PHY are the first IP cores to achieve compliance in UMC's 65-nanometer (nm) SP and LL process technologies. These immediately available IP cores are for System on Chip (SoC) devices used in portable hand-held convergence devices where USB2.0 is necessary for transferring media files at high speed and PCI express for motherboard level interface. Both DesignWare USB 2.0 nanoPHY IP and PCI Express 1.1 PHY feature tuning-circuits for post-silicon adjustments to take care of unexpected chip/board parasitics or process variations.
The DesignWare USB2.0 IP core consumes half the die space and power compared to previous IP cores from Synopsys.

The other USB IP Core providers in the market:
Taiwan based Faraday Technology also offers USB2.0 IP core but at 90nm process technology.

The USB 3.0 is the latest version in USB interface with far higher speeds than USB2.0. The vendors offering USB 3.0 IP core (Phy and device controller) are Gennum and Innovative Logic. Innovative Logic has announced USB 3.0 in Jan 09 and Gennum has released in this week of Mar 09.

Adopting ready to use off- the-shelf IP cores is a growing trend among VLSI designers to bring SoC devices faster to the market but at the higher design cost.