Date: 18/02/2009

CMOS transmitter IC for 40Gbps optical transmission systems

Fujitsu has announced the development of the new 65-nanometer (65nm) standard CMOS technology-based transmitter IC (serializer) for 40Gbps trunk-line optical transmission systems. New circuit technologies were developed, for the high-speed signal generation circuits capable of handling 40Gbps transmissions and for stable generation of 40Gbps output signals, within power voltage fluctuation ranges required for practical use.

In fact this CMOS-based transmitter for optical transmission systems integrates the I/O interface, signal processing, and high-speed signal generation that are all necessary for 40Gbps transmissions.

In order to employ CMOS technology to enable high-speed operation in the signal-generating circuitry and to realize output of 40Gbps output waveforms at qualities equivalent to those generated by compound semiconductors, not only does the operational speeds of data-transmitting circuits need to be accelerated, but the clock signals, which are provided to circuits to determine their operational timing, must operate at 20GHz with low noise and sufficient amplitude.
One major cause of amplitude degradation as the clock signals are distributed to the circuit is parasitic capacitance, from interconnects and elements. Due to the fact that CMOS has higher parasitic capacitance than compound semiconductors, in order to suppress amplitude degradation of clock signals at 20GHz, it is essential that the impact from parasitic capacitance be minimized. Furthermore, miniaturization of transistors as a means for higher performance also results in lowering of their breakdown voltage, thus limiting the usable power-supply voltage to a low 1V to 1.2 V. This means that a fluctuation in the power-supply could prevent sufficient voltage from reaching the circuit, thereby disrupting stable operation.

The newly developed technology features:

1. A new circuit technology was developed for the clock-distribution circuit in the transmitter IC, with which loss of clock signal swing is compensated by using inductors and low-power distribution of a low-noise clock signal becomes possible. Conventionally, to minimize the effects of parasitic capacitance, compensation using inductors to cancel capacitance have been used. By focusing on the fact that clock signals in the transmitter IC use a single frequency, new high-speed technology was used in which the inductor compensates for the parasitic capacitance only in the frequency band around the signal frequency.
2. A new circuit technology has been applied to the output circuit, with which timing of the clock signal, which controls circuit operation and the data signal, which passes through the circuit, is continually monitored in order to optimize the relationship between the two signals. In this circuit technology, the monitoring and adjusting mechanisms are segregated from the data-signal transmission pathway, so that additional circuits needed to implement these mechanisms do not degrade the data-signal waveform.
3. One-chip integration and new clock-distribution circuitry permit power consumption to be lowered to less than 2W. Since low-power operation reduces heat generation, it permits higher-density mounting of optical transceiver modules in optical transmission equipment. Compared to conventional 40Gbps equipment new transponders made using this technology will be roughly half the size, resulting in lower overall cost.
4. This transmitter IC uses the SFI5.2 interface, which has emerged as a standard for low-speed interfaces. By taking advantage of high-integration capabilities available in CMOS technology, the transmitter IC also has ability to output two 20Gbps signals in order to support a signal modulation technique intended for long-distance transmissions.

For more details visit the website: www.fujitsu.com