Date: 16/12/2008

FPGA design tool suite with advanced place and route algorithms

Lattice Semiconductor announced Version 7.2 of its ispLEVER FPGA design tool suite with advanced place and route algorithms that can deliver higher performance results. The ispLEVER 7.2 software also supports Lattice's "clock boosting" flow for the LatticeECP2 and LatticeECP2M FPGA families. Clock boosting can result in up to a 5% increase in FMax with no additional user input.

In addition to performance improvements, ispLEVER Version 7.2 continues to improve designers' productivity with additional control, analysis and workflow enhancements, and includes the latest release of Synopsys' Synplify Pro advanced FPGA synthesis solution.

Some of the key features are:

1. Using the new place and route techniques, ispLEVER software can analyze a design and automatically choose the most appropriate algorithm for the design's topology.
2. Properly constrained clock domains and cross-domain data-paths are critical to closing timing in today's multi-clock designs.
3. The Trace static timing analysis report now includes a "clock domain analysis" section. This is very useful for understanding the nature of the clock domains in the design, how they are currently constrained, where there are gaps in the constraint set and the datapaths that exist between the clock domains.
4. The ispLEVER 7.2-tool suite gives more user control over the use of Global Set/Reset routing. This can result in improved routability and performance for designs with demanding routing requirements.
5. The messages issued by the software's project navigator may be traced through a mouse click directly to the related line of source text opened in the user's favorite editor.
6. The source files may be imported using a list file, which eases the sharing of files between design tools.
7. In short the ispLEVER Design Tool Suite provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more.


Availability: The ispLEVER 7.2 for Windows, Linux and UNIX users is available immediately without charge for customers with active design tool maintenance.

Pricing: The full ispLEVER design tool suite is priced at $1295 for the Windows version.

For more information, visit www.latticesemi.com