Date: 08/11/2008

Altera releases Quartus II software version 8.1

Altera Corporation has unveiled Quartus® II software version 8.1.
New Features in Quartus II Software Version 8.1are,

1. SignalTap II Embedded Logic Analyzer - Finer data-sampling control speeds debugging and improves on-chip memory efficiency.

2. Enhanced SOPC Builder Tool-New HDL templates enhance the speed and ease for which SOPC Builder can be used for intellectual property (IP) reuse.

3. A new Avalon memory-mapped half-rate bridge is available for low-latency access for DDR SDRAMs.

4. New operating system support - Red Hat Enterprise Linux 5 and CentOS 4/5 (32 bit/64 bit) are now included.

5. Enhanced third-party simulation interface - The interface supports automatic compilation of library files for faster simulation setup.

6. New Pin-Out Advisor - The advisor guides pin-out creation and interface with third-party board tools.

7. Real Intent Verification Support - Real Intent's Meridian FPGA Clock Domain Crossing (CDC) software offers easy-to-use automatic clock intent verification to catch design errors and create confidence in reliable CDC operations.

8. New and enhanced IP cores and megafunctions - Digital signal processing (DSP), memory and protocols accelerate development.

9. Physical synthesis engine enhancements - Improve performance of timing-critical blocks in 20 percent less time on average than the previous version for faster timing closure.

10. Synopsys Design Constraints (SDC) - SDC templates guide and accelerate timing constraint creation.

Pricing and Availability
Both the subscription edition and the free web edition of Quartus II software version 8.1 now are available for download.
The annual software subscription is $2,495 for a node-locked PC license and is available for purchase at Altera's eStore or from authorized distributors