Date: 28/05/2008

A new member is added to the SPEAr family of Customizable processor from ST Micro

Customizable SOC chip named SPEAr from ST Microelectronics provides both ASIC type flexibility and low-cost advantages of ASSP. With ARM core, this family includes advanced bus system, IPs for connectivity and memory interface. The customized user functions can be programmed into a configurable logic block. ST says "Its ingenious combination of ASSP and ASIC methods".

The newest member of this family integrates advanced ARM926EJ-S processor core with two 16K memory caches. This device is designed to run at 333MHz packs 300,000 configurable logic gates. This chip is manufactured using advanced 65nm process technology.
The memory interfaces supported are LP-DDR and DDR2. The IP portfolio includes Fast IrDA interface, Ethernet MAC, three USB2.0 ports with embedded PHYs, UART, SPI, I2C, up to 102 fully programmable GPIOs and a total of 72 Kbytes of SRAM and 32 Kbytes of Boot ROM.

The targeted applications are, entry-level printers, fax machines, digital photo frames, Voice-over-IP and other equipment.

The printer related support features available are, image-pipeline accelerators, from color-space conversion to raster-file generation, a rotation engine, a hardware JPEG codec, an LCD controller (up to 1024x768, 24-bits per pixel) and a SDIO/MM card interface.

The other remaining features are, 10-bit analog-to-digital converter, a crypto accelerator based on ST's proprietary C3 IP, a Flexible Static Memory controller (NOR/NAND Flash and SRAM), TDM (Time-Division Multiplexing) and SLIC (Serial Link and Interrupt) controllers and a camera interface.

The operating systems supported are, Linux, VxWorks, ThreadX and Windows CE.

ST provides advanced development kit where the designer can thoroughly develop and test his product for all the criteria.


Availability: Now in samples
Cost: 6 US$ each per min order 20k pieces

For more details please visit www.st.com/spear