Date: 26/01/2010
Synopsys expands DesignWare MIPI IP portfolio for mobile devices
Synopsys has expanded its DesignWare Mobile Industry Processor Interface (MIPI) IP portfolio with 3G DigRF Controllers and PHY, Camera Serial Interface 2 (CSI-2) Host Controller, and D-PHY solutions that accelerates the development of mobile devices.
The MIPI Alliance defines a set of standard hardware interfaces between mobile baseband processors, RF integrated circuits (ICs) and peripherals found in smartphones and multimedia handheld devices.
Synopsys high-speed interfaces, and its DigRF, CSI-2 and D-PHY solutions enable baseband ICs and application processors to quickly integrate high-quality MIPI interfaces into complex SoCs with less risk.
The DesignWare 3G DigRF IP solution consisting of controllers, dual-mode PHY and verification environments to enable easy integration of the MIPI DigRF v3 standard in both digital baseband and RF ICs. The PHY includes an analog phase-locked loop (PLL) developed as a hard IP block to ensure the integrity of the high-speed clocks and signals required to meet the strict timing requirements of the protocol.
The MIPI CSI-2 specification provides a low-power, low pin count interface between camera sensors and application processors. The DesignWare CSI-2 Host Controller is configurable from one to four data lanes for a total throughput of up to 4 Gbps. Complementing the CSI-2 host controller is the DesignWare MIPI D-PHY, which is an integrated hard macro available as a unidirectional or a bi-directional PHY.
The unidirectional configuration is optimized to enable the implementation of compact and low power CSI-2 host applications. The bi-directional configuration enables a single PHY to support multiple MIPI interfaces, simplifying the development of designs implementing multiple MIPI interfaces such as CSI-2, DSI and UniPro. Delivering up to 1 Gbps per lane, the DesignWare MIPI D-PHY meets the bandwidth demands of advanced cameras and display peripherals on 65-nm and 40-nm nodes.
"As a leading provider of open market ASIC solutions working with multiple foundries, sourcing high-quality IP is key to our success," said Shri Gokhale, chief operating officer at Open-Silicon. "The Synopsys DesignWare 3G DigRF IP enabled us to focus on our core competencies and successfully service our customer with a product that can easily interface with leading RF ICs in the market. As one of the first members of Synopsys' IP OEM partner program, Open-Silicon is able to tightly integrate our engineers with the Synopsys IP engineering teams, allowing for a best-in-class IP integration experience for our customers."
"MIPI has become the de-facto industry standard for chip-to-chip interfaces within mobile terminals," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "With the addition of silicon-proven CSI-2, DigRF and D-PHY to the DesignWare IP portfolio, designers can now turn to a single, trusted vendor to help them successfully develop innovative mobile designs using MIPI interfaces with significantly less risk."
Availability: Now
For more details visit www.synopsys.com/designware