Date: 20/01/2010
Synposys offering protocol analyzer for verification of USB 3.0 designs
Synopsys has made available the DesignWare USB 3.0 Protocol Analyzer, a new graphical debugger for high speed USB 3.0. USB3.0 is 10 times improvement in speed compared to present USB 2.0.
The DesignWare USB 3.0 Protocol Analyzer offers graphical view of the data packets traffic of USB3.0 protocol. The designer can spot the any erroneous data flow pattern and can opt for viewing full packet information to find the right cause of fault.
The DesignWare USB 3.0 Protocol Analyzer is bundled with DesignWare verification IP for USB 3.0. This analyzer displays the protocol traffic generated from simulation runs using the DesignWare USB 3.0 verification IP transactors in a high-level color-coded summary view and a more detailed symbol-view of the individual packets and payloads. Debug is accelerated by allowing designers to distinguish and browse traffic types and switch between the two views. The DesignWare Verification IP for USB 3.0 supports Verilog testbenches, and constrained random methodologies as defined in the proven Verification Methodology Manual (VMM) for SystemVerilog.
"The DesignWare Protocol Analyzer allows us to browse protocol activity and makes it much faster and easier to debug protocol errors and latency issues," said Jessy Chen, executive vice president of Realtek. "As we develop and bring SuperSpeed USB 3.0 integrated products to the market, it is important that our engineers have the right tools to accelerate investigation of protocol behavior."
"Verification engineers are faced with tremendous challenges as standard interfaces on SoC designs increase in number and complexity," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By easing the verification effort with the new DesignWare Protocol Analyzer, Synopsys is leading the effort to help Realtek and other early providers of USB 3.0 solutions bring innovative products to market faster and with less risk."
Synopsys has also made available USB 3.0 transaction-level models (TLM) supporting the Open SystemC Initiative (OSCI) TLM-2.0 API specification. The models are TLM representations of the Synopsys DesignWare SuperSpeed USB 3.0 Device and xHCI Host Controller IP. The SuperSpeed USB 3.0 models enable pre-RTL and pre-silicon software development, verification and architecture exploration. They are part of the DesignWare System-Level Library which features more than 100 TLM models, including models of the DesignWare Interface IP portfolio.
USB3.0 interface may become more important in media processing chips due to immense bandwidth required for transferring HD quality video and audio in/out of the chip.
Availability: Now
For more info visit: ww.synopsys.com/usb3