Date: 29/12/2009

RTL simulator from Aldec with enhanced Assertions and Xilinx SecureIP support

Aldec has released Active-HDL 8.2 sp1, a new RTL and gate-level simulator for FPGA design and verification.

Active-HDL 8.2 sp1 includes support for Xilinx SecureIP, IEEE VHDL/Verilog encrypted IP and an enhanced Assertions bundle option. The new Assertion bundle supports three Assertion types are IEEE 1800 SystemVerilog Assertions (SVA), Property Description Language (PSL) and Open Vera Assertions (OVA) for legacy designs.

The bundle also supports Assertions Viewer, Assertion debugging and complete visibility of Assertions, properties and Functional Coverage statements through the simulator.

Availability:
Active-HDL 8.2 sp1: Now

For more details visit www.aldec.com