Date: 26/11/2009

Low-cost Linux RTL and Gate-level simulator from Aldec

Aldec has announced a low-cost Riviera-PRO LV, a multi-platform RTL and gate-level simulator that supports, IEEE VHDL, Verilog and SystemVerilog (Design) IEEE standard, Xilinx SecureIP and VHDL/Verilog IP encryption. The multi-platform simulator also supports both Linux and Windows.

The new configuration has no limitations on ASIC or FPGA device support and includes an advanced waveform toolset and fast debugging.

Availability: Riviera-PRO LV is available today as a perpetual or time-based floating license, time-based pricing starts under $5,000

For more details visit www.aldec.com/products/rivierapro