Date: 20/10/2009

IF sampling receiver subsystem from National Semiconductor for wireless basestations

National Semiconductor has introduced the SP16160CH1RB, an intermediate frequency (IF) sampling receiver reference design subsystem that provides signal amplification, digitization and clocking as used in wireless infrastructure systems, and suitable for multi-carrier, multi-standard wireless basestations addressing GSM/EDGE, WCDMA, LTE and WiMAX standards.

The subsystem reference design kit offers reference design board, software, schematic, bill of materials (BOM) and Gerber files - to accelerate the design and development of high-performance radio receivers.

The SP16160CH1RB operates from a single 5V supply and includes the dual-channel ADC16DV160 16-bit, 160 mega-samples per second (MSPS) pipeline ADC, dual-channel LMH6517 Digitally-controlled, Variable Gain Amplifier (DVGA), and LMK04031B clock jitter cleaner. The overall performance of the reference design is enabled by the high dynamic performance of the ADC, the low-noise and high-linearity of the DVGA and ultra-low rms jitter of the clock jitter cleaner.

The key features of the SP16160CH1RB reference design board are,

Delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF.
Configured with a low-noise, 153.6 MSPS CMOS sampling clock.
The ADC16DV160 delivers a signal-to-noise ratio (SNR) of 76.3 dBFS and SFDR of 91.2 dBFS at 192 MHz input IF.
The LMH6517 Digitally-controlled, Variable Gain Amplifier (DVGA) provides a noise figure of 6 dB and OIP3 of 45 dBm.
The LMK04031B clock jitter cleaner offers 150 fsec of rms clock jitter.
WaveVision 5.1 data capture board and WaveVision 5 software are available for National to speed up the design based on this chip.

Price:
The SP16160CH1RB subsystem reference design kit priced at each $995
Availability: Now

For more details visit www.national.com

Editorial Product Rating: Average Plus