Date: 17/09/2009

Cortex-A9 dual core processor with 2GHz capability from ARM

ARM has announced that the development of two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process, enabling a low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz.

Advanced physical IP techniques have enabled critical circuits within the design to be replaced with high tuned logic cells and memories, increasing performance while lowering overall power consumption.

The Cortex-A9 delivers its performance of 4000 DMIPS with power less than 250mW per CPU when selected from typical silicon, and also includes ARM AMBA-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area. Each Cortex-A9 with CoreSight Program Trace Macrocell (PTM), which provides full visibility into the processor's instruction flow, enabling the software community to develop code for optimal performance.

"The Cortex-A9 MPCore processor has already been widely accepted as the processor of choice for high-performance embedded applications across a broad spectrum of demanding consumer and enterprise devices," said Eric Schorn, VP marketing, Processor Division, ARM. "ARM's parallel development of advanced, optimized physical IP components demonstrates a new level of collaborative differentiation while enabling our Partners to expand their penetration into high margin domains traditionally occupied by proprietary architectures."

"ARM's long-standing investment in low-power leadership and ability to develop such high-performance devices enables licensees to lower the cost and risk of entering the high-margin markets currently addressed with competing proprietary solutions," said Will Strauss, principal analyst at Forward Concepts. "With single-thread performance capable of supporting very intensive workloads, the unprecedented level of power efficiency will enable licensees to introduce compelling new products."

"ARM and TSMC have enjoyed a long standing relationship of collaboration to ensure the development and delivery of best-in-class products optimized for our manufacturing process," said ST Juang, Sr. Director, Design Infrastructure Marketing Division, TSMC. "This provides OEMs developing feature-rich consumer and enterprise devices access to TSMC's manufacturing excellence and the power of ARM processor IP"

Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.

Availability: From the fourth quarter of 2009

From more details visit www.arm.com