Date: 10/09/2009

Synopsys DDR3 IP supports 2133 Mbps data rates and 1.35V DDR3L

Synopsys has announced that it's DesignWare DDR3/2 PHY and digital controller IP supports the 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard. The DDR3/2 PHY also supports the DDR3L specification that runs at 1.35V, making the DesignWare IP ideal for power-conscious designs. And targeted for high-performance applications such as digital home, digital office, data center and storage that all require bandwidth in excess of 1066 Mbps per pin.

To support the DDR3 data rates, the DesignWare DDR3/2 IP includes a unique PHY Utility Block with built-in data training circuits to enable in-system calibration, providing optimized system-level timing. As part of the data training sequence, the DDR3/2 IP includes the ability to remove bit-to-bit timing skew that can occur on the chip, in the package or on the circuit board. Removing the timing skew is necessary to achieve reliable system-level performance at data rates above 1066Mbps.

The DesignWare DDR3/2 PHY provides designers with a choice of interfaces to the memory controller IP. For the low latency interface, designers can utilize the complementary DesignWare DDR3/2 Memory Controller or Protocol Controller IP. The DesignWare DDR3/2 IP is a part of complete DesignWare DDR IP that consists of digital controllers, PHY and verification IP supporting DDR2, DDR3 and Mobile DDR. The comprehensive portfolio of DDR IP supports leading 130nm, 90nm, 65nm, 55nm and 45/40nm technologies.

"High-speed DDR interfaces represent a unique challenge for today's SoC designs," said Jim Finnegan, senior vice president of silicon engineering at Netronome Systems. "The high-quality DesignWare DDR3/2 PHY and controller IP allowed us to achieve our design objectives and Synopsys provided Netronome with access to a team of DDR experts that was invaluable as we pushed towards the completion of our latest chip design."

"DDR3 SDRAMs are rapidly evolving to offer both higher performance and lower power consumption," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "By providing early access to enhancements in the JEDEC standard DRAM roadmap, Synopsys is enabling designers to take full advantage of the latest advances in DDR technology. With a proven track record of over 200 DRAM interface design wins with more than 150 companies, Synopsys offers a low-risk path to working silicon."

Availability:
DesignWare DDR3/2 PHY: Now
DesignWare DDR3/2 controllers: From October 2009

For more details visit www.synopsys.com