Date: 26/05/2010

ST is ready with 32nm high-K metal tech for ASIC chips

ST Microelectronics is ready with 32-nanometer (nm) technology platform for the design and development of application-specific integrated circuits (ASICs) for networking applications. The Serializer-Deserializer (SerDes) IP is now available in 32nm 'bulk' silicon and its new 32nm SoC design platform implements ST's 32LPH (Low-Power High-performance) process technology for ASIC designs of greater than 200mm2.

ST says that the platform is designed to accelerate the development of next-generation networking ASICs used in high-performance applications such as enterprise switches, routers and servers as well as optical cross-connect and wireless infrastructure applications.

ST's 32LPH design platform supports up to 10 metallization layers to increase routing efficiency. The platform is based on the 32nm High-K Metal Gate process developed within the framework of the ISDA alliance. This platform incorporates specific IP and devices from ST, such as embedded DRAM with 10-Mbit per square millimeter density and Ternary Content Address Memory (TCAM).

"With the introduction of the 32LPH platform, ST is enabling the next generation of equipment for communication infrastructure applications, which requires highly integrated ASICs that can satisfy the increasing demand in performance, while also meeting extremely challenging power consumption and silicon integration goals," said Riccardo Ferrari, Group Vice President and General Manager of ST's Networking and Storage Division. "We are extremely encouraged by the strong interest that customers are demonstrating for this platform, which has already gained key design wins."

ST has a SerDes IP called S12, which ST claims is a key piece of intellectual property that has already been successfully demonstrated in labs at selected key customers. This IP is also claimed to be vital for the development of ASICs for networking applications and enables chip-to-chip, chip-to-module and backplane communications in networking equipment designs.

ST's S12 IP macro, is based on ST's SerDes architecture. It can be scaled up to eight 12.5-Gbit/s transmit/receive (Tx/Rx) channels per macro. The S12 has been designed with an optimal footprint for flip-chip BGA packages.

"ST is the first silicon supplier to bring a full design platform in a 32nm bulk-silicon process technology to the communication infrastructure market, including a next-generation predictive ASIC top-down design methodology, together with a full set of proven IP, such as a SerDes and embedded DRAM, successfully developed over many years by ST in previous technology nodes," said Philippe Magarshack, Technology R&D Group Vice-President, Central CAD & Design Solutions GM, STMicroelectronics. "ST's Technology R&D center in Crolles, France, has been instrumental in accelerating the completion of the 32LPH platform where low-power technology meets the high-performance requirements of networking applications, while still enjoying all the cost benefits of high-volume manufacturing. In addition, we have partnered with selected EDA vendors to offer networking customers the benefits of a predictable ASIC turnaround time, including fast virtual physical prototyping, and 32nm-class timing, signal and power integrity sign-off."

Availability: ASIC prototypes implemented in ST's 32LPH process technology are expected early in 2011

For more information visit: www.st.com.